Multilevel electronic interconnect structures for a variety of applications, particularly for forming integrated circuit chips, are well known in the art. These interconnect structures generally include several layers of conductors arranged in a predefined pattern separated by suitable insulating materials with vias for interconnection between layers. These structures may be used for manufacturing multi- or single chip module substrates, microelectronic passive devices (inductors, capacitors or combined circuitry) and interlevel structures for integrated circuits. Many electronic systems in fields such as the military, avionics, automotive, telecommunications, computers and portable electronics utilize components containing such structures.
One important use for these interconnect structures is Multi Chip Modules (MCM). The most advanced type of MCM technology is the so-called MCM-D technology, which provides modules whose interconnections are formed by the thin film deposition of metals on deposited dielectrics, which may be polymers or inorganic dielectrics. Using conventional fabrication techniques, MCMs can be produced having lines and spaces as thin as 10 .mu.m with vias down to 20 .mu.m in diameter. This MCM-D technology is unique because it achieves much higher interconnection density than other technologies. With the increase in density come equivalent improvements in signal propagation speed and overall device weight unmatched by other conventional means.
A schematic cross-section of a conventional MCM-D, indicated by reference numeral 10, is shown in FIG. 1. MCM 10 includes a base 11, generally formed of a dielectric material, a first metal layer 12 which serves as ground, a second metal layer 14 which serves to provide power to the MCM, and a layer of dielectric material 16, separating first metal layer 12 from second metal layer 14. MCM 10 includes two layers of conductors, 20 and 24, connected to metal layers 12 and 14, and connected to one another by vias 22. Dielectric material 16 separates the various metal elements.
A single chip 30 is shown affixed, by means of chip adhesive 28, to the upper surface of the multilevel interconnect structure thus formed. Chip 30 is coupled to a conductor 24' by a chip interconnect 32. It will be appreciated that in a complete MCM-D, a large number of layers of conductors coupled by vias are provided, and a large number of chips 30 are coupled to the multilevel interconnect portion of the module. Alternatively, chips can be placed in wells or openings in the surface of the interconnection layers to lower the thickness of the total package.
A number of techniques are known for producing electronic interconnect vias in MCM-D structures. According to one process, a dielectric material, generally ceramic or silicon coated with silicon dioxide, is provided as a base. Conductors are formed on the base beneath the dielectric material. A hole is formed in the dielectric material, which is then sputtered and pattern plated with a metal, such as copper, to interconnect the lower level of conductor 42 with a formed upper level 42. The vias 40 formed in this manner are known as unfilled vias, since the metal does not fill the entire hole, as shown in FIG. 2a. As can be seen in FIG. 1, the upper surface of dielectric material 18 above the unfilled vias is not planar. This is due to settling of the dielectric material in vias 22. In this case, the non-planar surface will reduce the conductors' density on the upper metal layer 42 and the unfilled via will decrease the via capability to remove heat generated by the chip.
According to another process, a thick photoresist layer is applied on top of the lower conductor level 46, as shown in FIG. 2b. The photoresist is patterned to define the vias, and metal, such as copper, is plated up 44. Photoresist is removed and polymer dielectric material is applied to cover conductors and vias. In the next step, the polymer is removed to expose the plated via and upper conductor level is applied 46. The vias 44 formed in this manner are known as filled vias, as shown in FIG. 2b. While filled vias are more desirable from a thermal and electrical point of view than unfilled vias, this process is complicated and expensive. This pattern plating process uses a thick layer of expensive photoresist, or an expensive photosensitive dielectric, and usually results in variation in the deposited metal thickness across the substrate. In this case, a non-masking dry etch back process to remove the polymer and expose the filled vias might not be applicable and additional steps, such as hard or soft mask etching processes or chemical mechanical polishing (CMP) may be required. This increases the number of process steps, and the equipment cost, and reduces the ability to process large area panels.
Yet another process is described in U.S. Pat. No. 5,580,825 to Labunov, et al. This process utilizes aluminum for the conductors and vias, and aluminum oxide as the dielectric material. The process includes defining level conductive paths by forming a blocking mask on the main aluminum layer, the blocking mask leaving exposed areas corresponding to the level conductive paths, carrying out a barrier anodization process on the main aluminum layer to form a surface barrier oxide over the level conductive paths, removing the blocking mask, providing an upper aluminum layer over the main aluminum layer, defining interlevel interconnections by forming a blocking mask on the upper aluminum layer, the blocking mask covering areas corresponding to the interlevel interconnections, and subjecting the main and upper aluminum layers to porous anodization. The barrier oxide defining the level conductive paths provides reliable masking of the level conductive paths during porous anodization. The porous aluminum oxide provides intralevel insulation between level conductive paths, and the combination of the barrier oxide and porous oxide provides reliable interlevel insulation between level conductive paths. The vias formed by this method are filled and the process results in a high degree of planarization.
It has now been found that other dielectric materials provide better performance than aluminum oxide, and that it is possible to provide, at reasonable cost, planarized filled aluminum vias with substantially perpendicular side walls formed by an overall environmentally friendly process. This provides an electronic interconnect structure which is relatively straightforward and inexpensive to manufacture, and which has high density interconnectivity and permits a stacked vias configuration.